The present invention relates to memory devices, and, in particular, those devices which employ parallel test features.
Conventional memory devices, for example static random access memories (SRAMs) and dynamic random access memories (DRAMs), as are commonly used in computer systems, often include parallel test features. Such features allow a manufacturer to test the memory cells of the device more quickly. In general, each cell of the memory device is tested to determine whether it is functioning properly (i.e., whether it is properly retaining a stored state). For large memories (e.g., on the order of 1 Megabit or more), parallel testing allows multiple cells (or bits) of the memory to be tested at the same time. For example, instead of having to test each cell individually, parallel test features incorporated into the memory or other programmable device may allow a manufacturer to test four, eight, sixteen, etc. cells at a time, thus reducing the overall test time for the device (a factor which has been recognized as being a significant portion of the overall production costs of a memory device).
Although such xe2x80x9cfunctionalxe2x80x9d (e.g., pass/fail) parallel testing for memory devices has been available (see, e.g., U.S. Pat. No. 5,383,157 entitled Parallel Testmode, assigned to the assignee of the present invention, the entire disclosure of which is incorporated herein by reference), such testing often provides no indication of the so-called critical path timing of the device under test in the case of an asynchronous memory. The xe2x80x9ccritical pathxe2x80x9d is the path through the device which determines the access time. For synchronous memory devices, the presence of input and output registers that are under the control of a common clock signal tends to set the timing parameters rather than the performance of any test circuitry. To illustrate, consider the synchronous memory 10 shown in FIG. 1. Input data 12 is applied to the input port of an input register 14 and is latched in the input register 14 in response to a clock signal 16. The data from input register 14 is written to a number of selected cells (e.g., four cells) of memory core 18 and the selected cells are programmed to retain the state of the data in signal 12. To test the functionality of the selected cells, the state of these cells is read by output register/test circuit 20 in response to a subsequent clock signal 16. Output register/test circuit 20 determines whether the state of each of the cells agrees with the state of the input data signal 12 and provides an indication of same as data out signal 22. Thus, data out signal 22 provides an indication as to whether there were any functional failures of the selected cells of memory core 18.
The signals from memory core 18 are latched in output register/test circuit 20 in response to clock signal 16 before they are tested. Thus, even the slowest of these signals has a predetermined time to set up before it is tested. Any timing differences between these signals is effectively masked by clock signal 16. Thus it can be seen that it is possible to easily add test circuitry to synchronous memories without impacting access, or clock to data output, time. In the case of asynchronous memories, the test circuitry itself must be configured to ensure that critical path timing is unaffected when test modes are invoked.
In a related and application entitled xe2x80x9cParallel Test For Asynchronous Memoryxe2x80x9d, application Ser. No. 08/985,890, filed Dec. 5, 1997, by James Allen, John Silver and Keith Ford and assigned to the Assignee of the present invention, the complete disclosure of which is hereby incorporated by reference, an asynchronous memory with parallel test circuitry configured to provide a measure of a slowest bit access time for the device was described. This parallel test circuitry included first circuitry configured to receive logic signals from a plurality of memory cells and to provide first output signals indicative of logic states of the plurality of those cells. The parallel test circuitry also included second circuitry configured to receive the first output signals and to produce second output signals indicative of logic states of the first output signals therefrom. In one example, such parallel test circuitry was configured for use in the read path of the memory device, thus allowing the second output signals to be produced at the slowest bit access time.
FIG. 2 illustrates an asynchronous memory device 50 configured in accordance with the invention described in the above-cited co-pending application. Memory 50 is configured with parallel test circuitry which, as indicated above, can significantly reduce the time required to test the memory cells thereof and provide a measure of the access time of a slowest cell or bit. For this embodiment, memory 50 includes a memory core 52 arranged as North and South blocks, each block having a Far and a Middle quarter. Thus, memory core 52 includes Far North quarter 54, Middle North quarter 56, Middle South quarter 58 and Far South quarter 60. Also included in memory core 52 are North and South redundant blocks 62 and 64, respectively. North and South redundant blocks 62 and 64 (which may be arranged as redundant rows and/or columns) include memory cells which may be used to replace defective memory cells located in other quarters of memory core 52. Although not shown in individual detail, it should be appreciated that memory core 52 is made up of a number of individual memory cells, which may be conventional SRAM cells.
During a parallel test operation, test data is written to selected cells of memory core 52 by simultaneously activating multiple memory blocks, for example as described in U.S. Pat. No. 5,383,157. The data stored in these selected cells is read out and compared to the expected state as applied by the tester. This provides the functional test of the cells.
The parallel test circuitry for accomplishing the parallel test includes Far-Middle Multiplexers (FM MUX) 66a-66d and North-South Multiplexers (NS MUX) 68a-68b. In this context, the term multiplexer is used to describe the actions of the FM MUXs 66a-66d which receive logic signals from selected cells of respective quarters of memory core 52 and provide output signals indicative of the logic states of these cells. For example, FM MUX 66a may receive logic signal LQFN from a selected cell within Far-North quarter 54 and logic signal LQMN from a selected cell within Middle-North quarter 56. The logic complements of these signals (e.g., {overscore (LQFN)} and {overscore (LQMN)}) are received by FM MUX 66c. Logic signals LQFN and {overscore (LQFN)} correspond to the true and complement states of a selected memory cell within Far-North quarter 54 (e.g., as may be provided to true and complement bit lines coupled to a conventional SRAM cell). Similarly, logic signals LQMN and {overscore (LQMN)} correspond to the true and complement states of a selected cell in Middle-North quarter 56. Thus, each FM MUX 66a and 66c receives true or complement, respectively, logic signals from selected cells of Far- and Middle-North quarters 54 and 56.
Because the same data is written to the selected cells of Far- and Middle-North quarters 54 and 56, the logic states of signals LQFN and LQMN should be the same when read by FM MUX 66a. That is, if a logic xe2x80x9c1xe2x80x9d is written to the selected cells, signals LQFN and LQMN should both indicate that a xe2x80x9c1xe2x80x9d was stored in the selected cells when these signals are read by FM MUX 66a (at least if these selected cells are functioning properly). Similarly, the logic states of signals {overscore (LQFN)} and {overscore (LQMN)} should be the same when read by FM MUX 66c. The output signals GQN and {overscore (GQN)} produced by FM MUX 66a and 66c, respectively, are indicative of the logic states of the selected cells which provided logic signal pairs LQFN/{overscore (LQFN)} and LQMN/{overscore (LQMN)}.
In a similar fashion, FM MUX 66b provides output signal GQS from logic signals LQMS and LQFS. FM MUX 66d provides output signal {overscore (GQS)} from logic signals {overscore (LQMS)} and {overscore (LQFS)}. Logic signal pair LQMS/{overscore (LQMS)} corresponds to a selected cell in Middle-South quarter 58 while logic signal pair LQFS/{overscore (LQFS)} corresponds to a selected cell in Far-South quarter 60.
Where redundancy is used, any of the logic signals LQFN or LQMN may be replaced by a logic signal RQN from redundant block 62. In such a case, corresponding logic signals {overscore (LQFN)} or {overscore (LQMN)} will be replaced by logic signal {overscore (RQN)}. Similarly, if redundancy is used in the South block of memory core 52, any of signals LQMS or LQFS may be replaced by signal RQS and a corresponding signal {overscore (RQS)} will replace any of logic signals {overscore (LQMS)} or {overscore (LQFS)}.
Signals GQN and GQS are provided to NS MUX 68a which is configured to produce an output signal {overscore (CQ)}. Output signal {overscore (CQ)} is indicative of the logic states of signals GQN and GQS and is not merely a selection of one of these signals. Likewise, NS MUX 68b receives signals {overscore (GQN)} and {overscore (GQS)} and produces output signal CQ which is indicative of the logic states of {overscore (GQN)} and {overscore (GQS)}.
Signals CQ and {overscore (CQ)} are applied as input signals to output driver 70 which includes n-channel transistors 72 and 74. Output driver 70 is activated in response to these input signals and, depending on the respective states of these signals, will either drive the logic state of output pin 76 high or low (i.e., to a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d). In some cases, where signals CQ and {overscore (CQ)} are both at logic low, pin 76 will be undriven and therefore in a high impedance state. These various voltage levels (high, low and high impedance) are indicative of whether the selected cells of memory core 52 accessed during the parallel test have functioned correctly (e.g., have stored the proper state of the test signal) or have failed. Where each of the four selected cells have stored the same logic state, a logic 1 or 0 (depending on the logic state of the signal written to the selected cells) will be obtained at pin 76. Where one of the cells has stored a different logic state than the others, pin 76 will be set to high impedance. To determine which of the cells has stored the different logic state (i.e., which of the cells failed), each of the four selected cells may be tested on an individual basis, as in conventional testing operations.
Because FM MUXs 66a-66d and NS MUXs 68a-68b also form part of the regular read path circuitry for memory 50, the speed at which an output signal appears at pin 76 in response to a read command during the parallel test is the same as for a regular read operation. Thus, the parallel test circuitry is automatically configured to provide a measure of the slowest cell or bit access time of memory core 52. Between accesses of different locations, the output at pin 76 is set to high impedance (e.g., using circuitry not shown). In response to a read command (e.g., as indicated using conventional read and/or chip select signals), a timer may be started. The time which elapses from the moment the read command is initiated to the point at which the voltage at pin 76 is recognized as a logic 1 or 0 (which need not necessarily be a full rail voltage) is the time for the slowest bit of the four selected cells. For the entire memory 50, the slowest such time for all of the cells of memory core 52 may be regarded as the read access time of the memory 50.
A complete parallel test sequence is accomplished as follows. First, selected cells in each of the quarters 54, 56, 58 and 60 are written with data. For example, the cells may be written with a logic 1. The selected cells are then tested by reading out the stored values from the selected cells using the above described parallel test circuitry. For example, assuming all of the selected cells properly stored a logic 1, and no redundancy was used, signals LQFN, LQMN, LQMS and LQFS will each be logic high. Thus, the respective output signals GQN and GQS of FM MUXs 66a and 66b will be logic high. Signals GQN and GQS will be received by NS MUX 68a which will produce a logic low output signal {overscore (CQ)}. The logic low output signal {overscore (CQ)} is buffered and applied to the gate of transistor 74, turning this transistor off and decoupling pin 76 from the voltage source ground.
At the same time, signals {overscore (LQFN)}, {overscore (LQMN)}, {overscore (LQFS)} and {overscore (LQMS)} are logic low. These signals are received by FM MUXs 66c and 66d which produce logic low output signals {overscore (GQN)} and {overscore (GQS)} in response. Signals {overscore (GQN)} and {overscore (GQS)} are received by NS MUX 68b which produces logic high output signal CQ in response. Logic high output signal CQ is buffered and is applied to the gate of transistor 72, turning on this transistor and pulling the voltage at pin 76 to a logic high potential. A valid logic potential on pin 76 indicates that all four selected cells in memory core 52 have stored this same logic state. Thus a CQ or {overscore (CQ)} signal can only reach a logic xe2x80x9c1xe2x80x9d if both of the input logic signals to be compared are at xe2x80x9c0xe2x80x9d. Now since all the global data lines, GQ, {overscore (GQ)} go high between data transitions, it is the later of the lines to transition to xe2x80x9c0xe2x80x9d which determines the speed of the CQ/{overscore (CQ)} combined data lines. Also since the output pad 76 is at high impedance or undriven between transitions it is the CQ or {overscore (CQ)} signal going high which drives the output pad to a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d at the access time of the slowest bit. These cells would pass the functional or timing test if this state matches the state expected by the tester 112.
Tester 112 may be a conventional SRAM test device. These testers commonly couple the output pins of a memory device under test to a test voltage (e.g., Vtest). The test voltage is set at a voltage potential (e.g., 1.73 V). If the selected cells of memory core 52 all store the same logic state, the voltage at pin 76 will be pulled to a logic high or low potential (as described above). However, if one or more of the selected cells stores an incorrect logic state, transistors 72 and 74 will both be off, and the voltage at pin 76 will remain at approximately 1.73 V. This is an indication that at least one of the cells has failed to store the correct logic state and that each of the cells currently undergoing testing should be individually tested to determine which has/have failed. Note that if all 4 cells have the wrong state the output will be driven to this same state. This will be detected by the tester as the opposite of the expected data.
One potential drawback of the above-described scheme is that it requires the use of double-ended busses in the output data path in order to be able to encode a logic xe2x80x9c1xe2x80x9d (all bits xe2x80x9c1xe2x80x9d), logic xe2x80x9c0xe2x80x9d (all bits xe2x80x9c0xe2x80x9d) or tri-state (i.e., high impedance) (bits disagree) at the output. Such double-ended busses are simply not available in asynchronous memories that are configured with single-ended output data paths, as may be employed in ultra low power applications. Moreover, the above architecture requires the use of xe2x80x9cNxe2x80x9d bus slots in the periphery of the memory device to allow a comparison of adjacent memory areas. This yields a so-called 2N folding factor (the folding factor represents the number of groups into which a memory array is divided in a scheme where the array is partitioned into blocks and the blocks are grouped together). Where xe2x80x9cNxe2x80x9d exceeds approximately 4, this represents a significant number of metal line slots to be run to the periphery on a die and becomes prohibitive. Thus, what is needed is a parallel test scheme for asynchronous memory devices with single-ended output data paths that combines pass/fail and multiple bit XOR functions.
In one embodiment, an asynchronous memory device includes parallel test circuitry configured to interface with a single-ended output data path of the memory device and, in some cases, to provide a measure of a slowest cell access time for the memory device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the memory device and to provide first output signals indicative of logic states of the plurality of cells; and second circuitry configured to receive the first output signals and to produce a second output signal indicative of the logic states of the first output signals therefrom. For example, the first circuitry and the second circuitry may be configured as a wired NAND and wired NOR combination. In some cases, one or more of the cells may be included within a redundant row or column of the memory device.
The first circuitry may include one or more circuits, each including an input path from a first number of the plurality of cells and configured to provide at least one of the first output signals. The second circuitry may include logic circuitry configured to receive the first output signals and a control signal and to provide the second output signal. For example, the second circuitry may include an exclusive OR circuit coupled to receive the first output signals and to produce the second output signal.
In a further embodiment, a parallel test method is provided. The method includes reading a plurality of cells of an asynchronous memory device having a single-ended output data path in parallel; and producing an output signal indicative of a logical combination of logic states of the plurality of cells. The output signal may be produced at an access speed of the slowest of the plurality of cells. In general, producing the output signal involves receiving logic signals from the plurality of cells and providing first output signals indicative of logic states of the plurality of cells. Then, the first output signals may be received and a second output signal indicative of the logic states of the first output signals produced therefrom.
In yet another embodiment parallel test circuitry includes an input path configured to receive logic signals from cells of an asynchronous memory device having a single-ended output data path; and logic circuitry coupled to the input path and configured to produce an output signal indicative of logic states stored in the cells. The input path may include a plurality of logic gates coupled to receive logic signals from the cells and one or more internal control signals of the asynchronous memory device, and driver transistors coupled the logic gates. The logic circuitry may include an exclusive OR gate.